4399造梦西游3玉皇大帝:數字設計工程師

發布時間:2019年05月17日 13:05    發布者:KT咨詢
關鍵詞: 數字電路設計 , 數?;旌?/a> , 通信

玉皇大帝和王毋娘娘什么关系 www.cfwxe.club NO.499-【獵頭職位:上海需要一位   數字設計工程師】聯系人:Raymond-Chen,郵箱:[email protected],微信也可查詢職位了!打開手機微信,搜號碼“KTHR_COM”或查找微信公眾帳號“KT人才”或掃描以上二維碼即可添加,歡迎大家關注!

Job Description:

1.     Thisposition is for a digital/ASIC design engineer to build next-generationanalog/digital mixed SoC chips.

2.     Handlingevery aspect in ASIC design flow including architecture, RTL coding,Verification, Synthesis, DFT, STA and P&R.

3.        Participateinto the chip debug and validation.

Job Requirement:

1.     BSEEwith minimum 3-year of working experience or MSEE with minimum 1-year ofworking experience for starting position

2.     MSEEwith minimum 3-year of working experience for senior position.

3.     Excellentknowledge for ASIC design, such as MOS transistor, arithmetic structure(addition, multiplication), timing analysis, design for test, meta-stabilityand etc.

4.     Needfundamental understanding for digital signal processing, such as FIR/IIR filterstructure, digital error correction, decimation/interpolation and etc.

5.     Usageexperience (not all of them required) of industry-standard EDA tools, such asVCS/NC, Design Compiler, Primetime, Formality/Conformal and Tetramer/DFTcompiler.

6.     Experiencein bus design (SPI, I2C, AHB or AIX), data path design (Filter, correlation orCodec), SerDescontroller (PCS and MAC) and PHY (channel encoder/decoder) willbe a plus.

7.     Experiencein metrics driven verification methodology (system Verilog/UVM based) will be aplus.

8.        Experiencein every aspect of ASIC design will be a great plus.

福利:五險一金  年終獎金 KT二維碼最小版.jpg


歡迎分享本文,轉載請保留出處://www.cfwxe.club/thread-563577-1-1.html     【打印本頁】
您需要登錄后才可以發表評論 登錄 | 立即注冊

廠商推薦

相關文章

相關視頻演示

關于我們  -  服務條款  -  使用指南  -  站點地圖  -  友情鏈接  -  聯系我們
玉皇大帝和王毋娘娘什么关系 © 版權所有   京ICP備16069177號 | 京公網安備11010502021702
回頂部